 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| d a t a sh eet product speci?cation supersedes data of 1997 apr 01 file under integrated circuits, ic12 1997 dec 16 integrated circuits pcf2104x lcd controller/driver
1997 dec 16 2 philips semiconductors product speci?cation lcd controller/driver pcf2104x contents 1 features 2 applications 3 general description 3.1 packages 3.2 available types 4 ordering information 5 block diagram 6 pinning 7 pin functions 7.1 rs: register select (parallel control) 7.2 r/w: read/write (parallel control) 7.3 e: data bus clock (parallel control) 7.4 db0 to db7: data bus (parallel control) 7.5 c1 to c60: column driver outputs 7.6 r1 to r32: row driver outputs 7.7 vlcd: lcd power supply 7.8 osc: oscillator 7.9 scl: serial clock line 7.10 sda: serial data line 7.11 sa0: address pin 7.12 t1: test pad 8 functional description 8.1 lcd bias voltage generator 8.2 oscillator 8.3 external clock 8.4 power-on reset 8.5 registers 8.6 busy flag 8.7 address counter (ac) 8.8 display data ram (ddram) 8.9 character generator rom (cgrom) 8.10 character generator ram (cgram) 8.11 cursor control circuit 8.12 timing generator 8.13 lcd row and column drivers 8.14 programming of mux 1 : 16 displays with pcf2104x 8.15 programming of mux 1 : 32 displays with pcf2104x 8.16 reset function 9 instructions 9.1 clear display 9.2 return home 9.3 entry mode set 9.3.1 i/d 9.3.2 s 9.4 display on/off control 9.4.1 d 9.4.2 c 9.4.3 b 9.5 cursor/display shift 9.6 function set 9.6.1 dl (parallel mode only) 9.6.2 n, m 9.7 set cgram address 9.8 set ddram address 9.9 read busy flag and address 9.10 write data to cgram or ddram 9.11 read data from cgram or ddram 10 interface to microcontroller (parallel interface) 11 interface to microcontroller (i 2 c-bus interface) 11.1 characteristics of the i 2 c-bus 11.2 bit transfer 11.3 start and stop conditions 11.4 system configuration 11.5 acknowledge 11.6 i 2 c-bus protocol 12 limiting values 13 handling 14 dc characteristics 15 ac characteristics 16 timing diagrams 17 application information 17.1 8-bit operation, 2 12 display using internal reset 17.2 4-bit operation, 2 12 display using internal reset 17.3 8-bit operation, 2 24 display 17.4 i 2 c operation, 2 12 display 17.5 initializing by instruction 18 bonding pad locations 19 definitions 20 life support applications 21 purchase of philips i 2 c components 1997 dec 16 3 philips semiconductors product speci?cation lcd controller/driver pcf2104x 1 features single chip lcd controller/driver 1 or 2-line display of up to 24 characters per line, or 2 or 4 lines of up to 12 characters per line 5 7 character format plus cursor; 5 8 for kana (japanese syllabary) and user-defined symbols on-chip: C generation of intermediate lcd bias voltages C oscillator requires no external components (external clock also possible) display data ram: 80 characters character generator rom: 240 characters character generator ram: 16 characters 4 or 8-bit parallel bus or 2-wire i 2 c-bus interface cmos/ttl compatible 32 row, 60 column outputs mux rates 1 : 32 and 1 : 16 uses common 11 code instruction set logic supply voltage range, v dd - v ss : 2.5 to 6 v display supply voltage range, v dd - v lcd : 3.5 to 9 v low power consumption. i 2 c-bus address: 011101 sa0. 2 applications telecom equipment portable instruments point-of-sale terminals. 3 general description the pcf2104x integrated circuit is similar to the pcf2114x (described in the pcf2116 family data sheet) but does not contain the high voltage generator of that device. the pcf2104x is optimized for chip-on-glass applications. the x in pcf2104x represents a specific letter code for a character set in the character generator rom (cgrom). two standard character sets are currently available, specified by the letters c and l (see figs 5 and 6). other character sets are available on request. the pcf2104x is a low-power cmos lcd controller and driver, designed to drive a split screen dot matrix lcd display of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with a 5 8 dot format. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd bias voltages which results in a minimum of external components and lower system power consumption. to allow partial v dd shutdown the esd protection system of the scl and sda pins does not use a diode connected to v dd . the chip contains a character generator and displays alphanumeric and kana characters. the pcf2104x interfaces to most microcontrollers via a 4 or 8-bit bus, or via the 2-wire i 2 c-bus. 3.1 packages pcf2104xu/2; chip with bumps in tray pcf2104xu/7; chip with bumps on tape. for further details see chapter 18. 3.2 available types pcf2104cu/x: character set c in cgrom pcf2104lu/x: character set l in cgrom pcf2104nu/x: character set n in cgrom. 4 ordering information type number package name description version pcf2104cu/2 - chip with bumps in tray - pcf2104cu/7 - chip with bumps on tape - pcf2104lu/2 - chip with bumps in tray - pcf2104lu/7 - chip with bumps on tape - pcf2104nu/2 - chip with bumps in tray - pcf2104nu/7 - chip with bumps on tape - 1997 dec 16 4 philips semiconductors product speci?cation lcd controller/driver pcf2104x 5 block diagram fig.1 block diagram. handbook, full pagewidth shift register 32-bit mgc627 v ss v dd character generator ram (cgram) 16 characters character generator rom (cgrom) 240 characters cursor + data control 5 5 shift register 5 x 12-bit 60 data latches 60 column drivers 6 bias voltage generator 60 32 row drivers 8 display data ram (ddram) 80 characters 32 5-20 81-96 address counter (ac) instruction decoder instruction register (ir) data register (dr) busy flag 7 8 8 i/o buffer 8 7 7 8 2 111 4 v lcd display address counter power - on reset timing generator oscillator 7 1 osc c1 to c60 r1 to r32 4 109-106 4 98 100 99 db0 to db3 db4 to db7 e rs r/w pcf2104x 97 scl 110 sda 3 sa0 101 t1 105-102 80-21 1997 dec 16 5 philips semiconductors product speci?cation lcd controller/driver pcf2104x 6 pinning symbol ffc pad type description osc 1 i oscillator/external clock input v dd 2 p logic supply voltage sa0 3 i i 2 c-bus address pin input v ss 4 p ground r8 to r5 5 to 8 o lcd row driver outputs r32 to r29 9 to12 o lcd row driver outputs r24 to r17 13 to 20 o lcd row driver outputs c60 to c1 21 to 80 o lcd column driver outputs r9 to r16 81 to 88 o lcd row driver outputs r25 to r28 89 to 92 o lcd row driver outputs r1 to r4 93 to 96 o lcd row driver outputs scl 97 i i 2 c-bus serial clock input e 98 i data bus clock input rs 99 i register select input r/ w 100 i read/write input t1 101 i test pad input db7 to db0 102 to 109 i/o 8-bit bidirectional data bus input/output sda 110 i/o i 2 c-bus serial data input/output v lcd 111 i lcd supply voltage input 7 pin functions 7.1 rs: register select (parallel control) rs selects the register to be accessed for read and write when the device is controlled by the parallel interface. rs = logic 0 selects the instruction register for write and the busy flag and address counter for read. rs = logic 1 selects the data register for both read and write. there is an internal pull-up on pin rs. 7.2 r/ w: read/write (parallel control) r/ w selects either the read (r/ w = logic 1) or write (r/ w = logic 0) operation when control is by the parallel interface. there is an internal pull-up on this pin. 7.3 e: data bus clock (parallel control) the e pin is set high to signal the start of a read or write operation when the device is controlled by the parallel interface. data is clocked in or out of the chip on the negative edge of the clock. note that this pin must be tied to logic 0 (v ss ) when i 2 c-bus control is used. 7.4 db0 to db7: data bus (parallel control) the bidirectional, 3-state data bus transfers data between the system controller and the pcf2104x. db7 may be used as the busy flag, signalling that internal operations are not yet completed. in 4-bit operations the 4 higher order lines db4 to db7 are used; db0 to db3 must be left open circuit. there is an internal pull-up on each of the data lines. note that these pins must be left open circuit when i 2 c-bus control is used. 7.5 c1 to c60: column driver outputs these pins output the data for pairs of columns. this arrangement permits optimized chip-on-glass (cog) layout for 4-line by 12 characters. 7.6 r1 to r32: row driver outputs these pins output the row select waveforms to the left and right halves of the display. 7.7 v lcd : lcd power supply negative power supply for the liquid crystal display. 1997 dec 16 6 philips semiconductors product speci?cation lcd controller/driver pcf2104x 7.8 osc: oscillator when the on-chip oscillator is used, this pin must be connected to v dd . an external clock signal, if used, is input at this pin. 7.9 scl: serial clock line input for the i 2 c-bus clock signal. 7.10 sda: serial data line input/output for the i 2 c-bus data line. 7.11 sa0: address pin the hardware sub-address line is used to program the device sub-address for 2 different pcf2104xs on the same i 2 c-bus. 7.12 t1: test pad must be connected to v ss . not user accessible. 8 functional description (see fig.1) 8.1 lcd bias voltage generator the intermediate bias voltages for the lcd display are also generated on-chip. this removes the need for an external resistive bias chain and significantly reduces the system power consumption. the optimum levels depend on the multiplex rate and are selected automatically when the number of lines in the display is defined. the optimum value of v op depends on the multiplex rate, the lcd threshold voltage (v th ) and the number of bias levels. the relationships are given in table 1. using a 5-level bias scheme for 1 : 16 mux rate allows v op < 5 v for most lcd liquids. the effect on the display contrast is negligible. table 1 optimum values for v op mux rate number of bias levels v op /v th discrimination v on /v off 1 : 16 5 3.67 1.277 1 : 32 6 5.19 1.196 8.2 oscillator the on-chip oscillator provides the clock signal for the display system. no external components are required. pin osc must be connected to v dd . 8.3 external clock if an external clock is to be used, it must be input at pin osc. the resulting display frame frequency is given by f frame = 1 2304 f osc . a clock signal must always be present, otherwise the lcd may be frozen in a dc state. 8.4 power-on reset the power-on reset block initializes the chip after power-on or power failure. 8.5 registers the pcf2104x has two 8-bit registers, an instruction register (ir) and a data register (dr). the register select signal (rs) determines which register will be accessed. the instruction register stores instruction codes such as display clear and cursor shift, and address information for the display data ram (ddram) and character generator ram (cgram). the instruction register can be written to, but not read from, by the system controller. the data register temporarily stores data to be read from the ddram and cgram. when reading, data from the ddram or cgram (corresponding to the address in the address counter) is written to the data register prior to being read by the read data instruction. 8.6 busy flag the busy flag indicates the free/busy status of the pcf2104x. logic 1 indicates that the chip is busy and further instructions will not be accepted. the busy flag is output at pin db7 when rs = logic 0 and r/ w = logic 1. instructions should only be written after checking that the busy flag is at logic 0 or waiting for the required number of clock cycles. 1997 dec 16 7 philips semiconductors product speci?cation lcd controller/driver pcf2104x 8.7 address counter (ac) the address counter assigns addresses to the ddram and cgram for reading and writing and is set by the instructions set cgram address and set ddram address. after a read/write operation the address counter is automatically incremented or decremented by 1. the address counter contents are output to the bus (db0 to db6) when rs = logic 0 and r/ w = logic 1. 8.8 display data ram (ddram) the ddram stores up to 80 characters of display data, represented by 8-bit character codes. ddram locations not used for storing display data can be used as general purpose ram. the basic ddram-to-display mapping scheme is shown in fig.2. with no display shift, the characters represented by the codes in the first 12 or 24 ram locations, starting at address 00 in line 1, are displayed. subsequent lines display data starting at addresses 20, 40, or 60 hex. figures 3 and 4 show the ddram-to-display mapping scheme when the display is shifted. the address range for a 1-line display is 00 to 4f; for a 2-line display from 00 to 27 (line 1) and 40 to 67 (line 2); for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and 60 to 73 for lines 1, 2, 3 and 4 respectively. for 2 and 4-line displays the end address of one line and the start address of the next line are not consecutive. when the display is shifted each line wraps around independently of the others (see figs 3 and 4). when data is written to the ddram wrap-around occurs from 4f to 00 in 1-line mode and from 27 to 40 and 67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60 and 73 to 00 in 4-line mode. 8.9 character generator rom (cgrom) the character generator rom generates 240 character patterns in 5 8 dot format from 8-bit character codes. figures 5 and 6 show the character sets currently available. 8.10 character generator ram (cgram) up to 16 user-defined characters may be stored in the character generator ram. the cgrom and cgram use a common address space, of which the first column is reserved for the cgram (see fig.5). figure 8 shows the addressing principle for the cgram. 8.11 cursor control circuit the cursor control circuit generates the cursor (underline and/or character blink as shown in fig.9) at the ddram address contained in the address counter. when the address counter contains the cgram address the cursor will be inhibited. 8.12 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not disturbed by operations on the data buses. 8.13 lcd row and column drivers the pcf2104x contains 32 row and 60 column drivers, which connect the appropriate lcd bias voltages in sequence to the display, in accordance with the data to be displayed. the bias voltages and the timing are selected automatically when the number of lines in the display is selected. figures 10 and 11 show typical waveforms. in the 1-line mode (1 : 16) the row outputs are driven in pairs: r1/r17, r2/r18 for example. this allows the output pairs to be connected in parallel, thereby providing greater drive capability. unused outputs should be left unconnected. 1997 dec 16 8 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.2 ddram-to-display mapping; no shift (pcf2104x). handbook, 4 columns 12345 222324 00 01 02 03 04 15 16 17 18 19 4c 4d 4e 4f non-displayed ddram addresses display position (decimal) ddram address (hex) 1-line display 64 65 66 67 40 41 42 43 44 55 56 57 58 59 00 01 02 03 04 15 16 17 18 19 24 25 26 27 non-displayed ddram address ddram (hex) address 2-line display line 1 line 2 mla792 handbook, 4 columns 123456789101112 non-displayed ddram addresses ddram address (hex) 4 line display 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 line 1 line 2 line 3 line 4 mla793 1997 dec 16 9 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.3 ddram-to-display mapping; right shift (pcf2104x). 27 00 01 02 03 67 40 41 42 43 14 15 16 54 55 56 ddram address (hex) line 1 line 2 2-line display 1 2 3 4 5 22 23 24 4f 00 01 02 03 14 15 16 display position (decimal) ddram address (hex) 1-line display mla802 13 01 02 03 04 05 06 07 08 09 0a 20 21 22 23 24 25 26 27 28 29 2a 33 40 41 42 43 44 45 46 47 48 49 4a 53 60 61 62 63 64 65 66 67 68 69 6a 73 123456789101112 ddram address (hex) line 1 line 2 line 3 line 4 4-line display 00 mla803 fig.4 ddram-to-display mapping; left shift (pcf2104x). 1 2 3 4 5 22 23 24 05 01 02 03 04 16 17 18 41 42 43 44 45 56 57 58 05 01 02 03 04 16 17 18 display position (decimal) ddram address (hex) ddram address (hex) line 1 line 2 1-line display 2-line display mla815 01 02 03 04 05 06 07 08 09 0a 0b 0c 21 22 23 24 25 26 27 28 29 2a 2b 2c 41 42 43 44 45 46 47 48 49 4a 4b 4c 61 62 63 64 65 66 67 68 69 6a 6b 6c 123456789101112 ddram address (hex) line 1 line 2 line 3 line 4 4-line display mla816 1997 dec 16 10 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.5 character set c in cgrom; pcf2104c . handbook, full pagewidth mlb895 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 cg ram 1 1997 dec 16 11 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.6 character set l in cgrom; pcf2104l . handbook, full pagewidth mgc629 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 6 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 cg ram 1 1997 dec 16 12 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.7 character set n in cgrom; pcf2104n . handbook, full pagewidth mgm134 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 cg ram 1 1997 dec 16 13 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.8 relationship between cgram addresses, data and display patterns. handbook, full pagewidth mga800 - 1 76543210 6543210 43210 higher order bits lower order bits lower order bits higher order bits lower order bits higher order bits 00000000 0000000 0 001 000 010 000 011 0 100 0 00 101 00 0 110 000 111 00000 000 000 001 0 0 0 010 00 00 011 100 101 00 00 110 00 00 111 00000 001 00000001 0001 00000010 00001111 00001111 00001111 00001111 01 0 0000 100 101 110 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111 character codes (ddram data) cgram address character patterns (cgram data) character pattern example 1 cursor position character pattern example 2 character code bits 0 to 3 correspond to cgram address bits 3 to 6. cgram address bits 0 to 2 designate character pattern line position. the 8 th line is the cursor position and display is performed by logical or with the cursor. data in the 8 th line will appear in the cursor position. character pattern column positions correspond to cgram data bits 0 to 4; bit 4 being at the left end, as shown in the figure. cgram character patterns are selected when character code bits 4 to 7 are all logic 0. cgram data = logic 1 corresponds to selection f or display. only bits 0 to 5 of the cgram address are set by the set cgram address instruction. bit 6 can be set using the set ddram address instruction or by using the auto-increment feature during cgram write. all bits 0 to 6 can be read using the read busy flag and address instruc tion. 1997 dec 16 14 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.9 cursor and blink display examples. mga801 cursor 5 x 7 dot character font alternating display cursor display example blink display example 1997 dec 16 15 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.10 typical lcd waveforms; 1-line mode. handbook, full pagewidth mga802 - 1 v dd v 2 v v 5 lcd row 1 col 1 state 1 (on) state 2 (on) 0.25 v op 0 v state 1 1-line display (1:16) frame n 1 frame n row 9 row 2 col 2 state 2 123 16123 16 34 v /v v dd v 2 v v 5 lcd 34 v /v v dd v 2 v v 5 lcd 34 v /v v dd v 2 v v 5 lcd 34 v /v v dd v 2 v v 5 lcd 3 4 v /v 0.25 v op 0.25 v op 0 v 0.25 v op v op v op v op v op 1997 dec 16 16 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.11 typical lcd waveforms; 2-line mode. handbook, full pagewidth mga803 - 1 v dd v 2 v v v v 3 4 5 lcd row 1 v dd v 2 v v v v 3 4 5 lcd v dd v 2 v v v v 3 4 5 lcd col 1 v dd v 2 v v v v 3 4 5 lcd state 1 (on) state 2 (on) 0.15 v op 0 v v op v op v op state 1 2-line display (1:32) frame n 1 frame n row 9 row 2 col 2 v dd v 2 v v v v 3 4 5 lcd 0.15 v op 0.15 v op 0 v 0.15 v op v op state 2 123 3212 3 32 1997 dec 16 17 philips semiconductors product speci?cation lcd controller/driver pcf2104x 8.14 programming of mux 1 : 16 displays with pcf2104x the pcf2104x can be used in the following ways: 1-line mode to drive a 2-line display 2 12 characters with mux rate 1 : 16, resulting in better contrast. the internal data flow of the chip is optimized for this purpose. using the function set instruction, m and n are set to 0, 0 (respectively). figures 12, 13 and 14 show the ddram addresses of the display characters. the second row of each table corresponds to either the right half of a 1-line display or to the second line of a 2-line display. wrap around of data during display shift or when writing data is non-standard. fig.12 ddram-to-display mapping; no shift (pcf2104x). handbook, full pagewidth 00 01 02 03 04 05 06 07 08 09 0a 0b 1 23 4 5 67 8 9 10 11 12 mlb899 display position ddram address 0c 0d 0e 0f 10 11 12 13 14 15 16 17 13 14 15 16 17 18 19 20 21 22 23 24 display position ddram address fig.13 ddram-to-display mapping; right shift (pcf2104x). handbook, full pagewidth 4f 00 01 02 03 04 05 06 07 08 09 0a 1 23 4 5 67 8 9 10 11 12 mlb900 display position ddram address 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 13 14 15 16 17 18 19 20 21 22 23 24 display position ddram address handbook, full pagewidth 01 02 03 04 05 06 07 08 09 0a 0b 0c 1 23 4 5 67 8 9 10 11 12 mlb901 display position ddram address 0d 0e 0f 10 11 12 13 14 15 16 17 18 13 14 15 16 17 18 19 20 21 22 23 24 display position ddram address fig.14 ddram-to-display mapping; left shift (pcf2104x). 1997 dec 16 18 philips semiconductors product speci?cation lcd controller/driver pcf2104x 8.15 programming of mux 1 : 32 displays with pcf2104x to drive a 2-line by 24 characters mux 1 : 32 display, use instruction function set to set m, n to 0, 1 (respectively). to drive a 4-line by 12 characters mux 1:32 display, use instruction function set to set m, n to 1, 1 (respectively). 8.16 reset function the pcf2104 automatically initializes (resets) when power is turned on. the state after reset is given in table 2. table 2 state after reset step description 1 display clear. 2 function set: dl = 1: 8-bit interface m, n = 0 1-line display g = 0: not used 3 display on/off control: d = 0: display off c = 0: cursor off; b = 0: blink off; 4 entry mode set: i/d = 1: +1 (increment) g = 0: not used 5 default address pointer to ddram. the busy flag (bf) indicates the busy state (bf = logic 1) until initialization ends. the busy state lasts 2 ms. the chip may also be initialized by software. see tables 10 and 11. 6i 2 c-bus interface reset. 9 instructions only two pcf2104x registers, the instruction register (ir) and the data register (dr) can be directly controlled by the microcontroller. before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interfacing to peripheral control ics. the pcf2104x operation is controlled by the instructions shown in table 3 together with their execution time. details are explained in subsequent sections. instructions are of 4 categories, those that: 1. designate pcf2104x functions such as display format, data length, etc. 2. set internal ram addresses 3. perform data transfer with internal ram 4. others. in normal use, category 3 instructions are used most frequently. however, automatic incrementing by 1 (or decrementing by 1) of internal ram addresses after each data write lessens the microcontroller program load. the display shift in particular can be performed concurrently with display data write, thus enabling the designer to develop systems in minimum time with maximum programming efficiency. during internal operation, no instruction other than the busy flag/address read instruction will be executed. because the busy flag is set to logic 1 while an instruction is being executed, it is advisable to ensure that the flag it is at logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in table 3. an instruction sent while the busy flag is high will not be executed. 1997 dec 16 19 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 3 instructions (note 1) notes 1. in the i 2 c-bus mode the dl bit is don't care. 8-bit mode is assumed. in the i 2 c-bus mode a control byte is required when rs or r/ w is changed; control byte: co, rs, r/ w, 0, 0, 0, 0, 0; command byte: db7 to db0. 2. example: f osc = 150 khz, ; 3 cycles = 20 m s, 165 cycles = 1.1 ms. instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description required clock cycles (2) nop 0000000000no operation. 0 clear display 0 000000001 clears entire display and sets ddram address 0 in address counter. 165 return home 0 000000010 sets ddram address 0 in address counter also returns shifted display to original position ddram contents remain unchanged. 3 entry mode set 0 0000001i/ds sets cursor move direction and speci?es shift of display. these operations are performed during data write and read. 3 display control 0 000001dcb sets entire display on/off (d), cursor on/off (c) and blink of cursor position character (b). 3 cursor/display shift 0 00001s/cr/l00 moves cursor and shifts display without changing ddram contents. 3 function set 0 0001dlnmg0 sets interface data length (dl), number of display lines (n, m) and voltage generator control (g). 3 set cgram address 0001 a cg sets cgram address. 3 set ddram address 001 a dd sets ddram address. 3 read busy ?ag and address 0 1 bf a c reads busy flag (bf) indicating internal operation is being performed and reads address counter contents. 0 read data 1 1 read data reads data from cgram or ddram. 3 write data 1 0 write data writes data to cgram or ddram. 3 t cy 1 f osc --------- 6.67 m s == 1997 dec 16 20 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 4 command bit identities bit logic 0 logic 1 i/d decrement increment s display freeze display shift d display off display on c cursor off cursor on b character at cursor position does not blink character at cursor position blinks s/c cursor move display shift r/l left shift right shift dl 4 bits 8 bits n (m = 0) 2 line 12 characters; mux 1 : 16 2 lines 24 characters; mux 1 : 32 n (m = 1) reserved 4 lines 12 characters; mux 1 : 32 bf end of internal operation internal operation in progress co last control byte, only data bytes to follow next two bytes are a data byte and another control byte fig.15 4-bit transfer example. mga804 rs e db7 r/w db6 db5 db4 instruction write busy flag and address counter read data register read ir7 ir3 bf ac3 dr7 dr3 ir6 ir2 ac6 ac2 dr6 dr2 ir5 ir1 ac5 ac1 dr5 dr1 ir4 ir0 ac4 ac0 dr4 dr0 1997 dec 16 21 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.16 an example of 4-bit data transfer timing sequence. mga805 rs e internal db7 r/w internal operation ir7 ir3 ac3 d7 d3 not busy ac3 busy instruction write busy flag check busy flag check instruction write ir7, ir3: instruction 7 th bit, 3 rd bit. ac3: address counter 3 rd bit. fig.17 example of busy flag check timing sequence. mga806 instruction write busy flag check busy flag check busy flag check instruction write internal operation rs e internal db7 r/w data busy busy not busy data 1997 dec 16 22 philips semiconductors product speci?cation lcd controller/driver pcf2104x 9.1 clear display clear display writes space code 20 (hexadecimal) into all ddram addresses (the character pattern for character code 20 must be a blank pattern), sets the ddram address counter to logic 0 and returns the display to its original position if it was shifted. consequently, the display disappears and the cursor or blink position goes to the left edge of the display (the first line if 2 or 4 lines are displayed) and sets the entry mode to i/d = logic 1 (increment mode). s of entry mode does not change. the instruction clear display requires extra execution time. this may be allowed for by checking the busy flag (bf) or by waiting until 2 ms has elapsed. the latter must be applied where no read-back options are foreseen, as in some chip-on-glass (cog) applications. 9.2 return home return home sets the ddram address counter to logic 0 and returns the display to its original position if it was shifted. ddram contents do not change. the cursor or blink position goes to the left of the display (the first line if 2 or 4 lines are displayed). i/d and s of entry mode do not change. 9.3 entry mode set 9.3.1 i/d when i/d = logic 1 (0) the ddram or cgram address increments (decrements) by 1 when data is written to or read from the ddram or cgram. the cursor or blink position moves to the right when incremented and to the left when decremented. the cursor and blink are inhibited when the cgram is accessed. 9.3.2 s when s = logic 1, the entire display shifts either to the right (i/d = logic 0) or to the left (i/d = logic 1) during a ddram write. consequently, it looks as if the cursor stands still and the display moves. the display does not shift when reading from the ddram, or when writing to or reading from the cgram. when s = logic 0 the display does not shift. 9.4 display on/off control 9.4.1 d the display is on when d = logic 1 and off when d = logic 0. display data in the ddram is not affected and can be displayed immediately by setting d to logic 1. 9.4.2 c the cursor is displayed when c = logic 1 and inhibited when c = logic 0. even if the cursor disappears, the display functions i/d, etc. remain in operation during display data write. the cursor is displayed using 5 dots in the 8th line (see fig.9). 9.4.3 b the character indicated by the cursor blinks when b = logic 1. the blink is displayed by switching between display characters and all dots on with a period of 1 second when f osc = 150 khz (see fig.9). at other clock frequencies the blink period is equal to 150 khz/f osc . the cursor and the blink can be set to display simultaneously. 9.5 cursor/display shift cursor/display shift moves the cursor position or the display to the right or left without writing or reading display data. this function is used to correct a character or move the cursor through the display. in 2 or 4-line displays, the cursor moves to the next line when it passes the last position of the line (40 or 20 decimal). when the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. the address counter (ac) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift. 9.6 function set 9.6.1 dl ( parallel mode only ) sets interface data width. data is sent or received in bytes (db7 to db0) when dl = logic 1 or in two nibbles (db7 to db4) when dl = logic 0. when 4-bit width is selected, data is transmitted in two cycles using the parallel bus (1) . function set from i 2 c-bus interface: dl bit can not bet set to logic 0 from the i 2 c-bus interface. if bit dl has been set to logic 0 via the parallel bus, programming via the i 2 c-bus interface is complicated. 9.6.2 n, m sets number of display lines. (1) in a 4-bit application db3 to db0 are left open (internal pull-ups). hence in the ?rst function set instruction after power-on g and h are set to 1. a second function set must then be sent (2 nibbles) to set g and h to their required values. 1997 dec 16 23 philips semiconductors product speci?cation lcd controller/driver pcf2104x 9.7 set cgram address set cgram address sets bits 0 to 5 of the cgram address (a cg in table 3) into the address counter (binary a[5] to a[0]). data can then be written to or read from the cgram. only bits 0 to 5 of the cgram address are set by the set cgram address instruction. bit 6 can be set using the set ddram address instruction or by using the auto-increment feature during cgram write. all bits 0 to 6 can be read using the read busy flag and address instruction. 9.8 set ddram address set ddram address sets the ddram address (a dd in table 3) into the address counter (binary a[6] to a[0). data can then be written to or read from the ddram. table 5 hexadecimal address ranges 9.9 read busy ?ag and address read busy flag and address reads the busy flag (bf). when bf = logic 1 it indicates that an internal operation is in progress. the next instruction will not be executed until bf = logic 0, so bf should be checked before sending another instruction. at the same time, the value of the address counter expressed in binary a[6] to a[0] is read out. the address counter is used by both cgram and ddram and its value is determined by the previous instruction. 9.10 write data to cgram or ddram writes binary 8-bit data d[7] to d[0] to the cgram or the ddram. whether the cgram or ddram is to be written to is determined by the previous specification of cgram or ddram address setting. after writing, the address automatically increments or decrements by 1, in accordance with the entry mode. only bits d0 to d4 of cgram data are valid, bits d5 to d7 are don't care. address function 00 to 4f 1-line by 24 00 to 0b and 0c to 4f 2-line by 12 00 to 27 and 40 to 67 2-line by 24 00 to 13, 20 to 33, 40 to 53 and 60 to 73 4-line by 12 9.11 read data from cgram or ddram reads binary 8-bit data d[7] to d[0] from the cgram or ddram. the most recent set address instruction determines whether the cgram or ddram is to be read. the read data instruction gates the content of the data register (dr) to the bus while e = high. after e goes low again, internal operation increments (or decrements) the ac and stores ram data corresponding to the new ac into the dr. remark: the only three instructions that update the data register (dr) are: set cgram address set ddram address read data from cgram or ddram. other instructions (e.g. write data, cursor/display shift, clear display, return home) will not modify the data register content. 10 interface to microcontroller (parallel interface) the pcf2104x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. in the 8-bit mode data is transferred as 8-bit bytes using the 8 data lines db0 to db7. three further control lines e, rs, and r/ w are required. in the 4-bit mode data is transferred in two cycles of 4-bits each. the higher order bits (corresponding to db4 to db7 in 8-bit mode) are sent in the first cycle and the lower order bits (db0 to db3 in 8-bit mode) in the second cycle. data transfer is complete after two 4-bit data transfers. it should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction. see figs 15, 16 and 17 for examples of bus protocol. in the 4-bit mode pins db3 to db0 must be left open-circuit. they are pulled up to v dd internally. 1997 dec 16 24 philips semiconductors product speci?cation lcd controller/driver pcf2104x 11 interface to microcontroller (i 2 c-bus interface) 11.1 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 11.2 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 11.3 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). 11.4 system con?guration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. 11.5 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. 11.6 i 2 c-bus protocol before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always carried out with the first byte transmitted after the start procedure. the i 2 c-bus configuration for the different pcf2104x read and write cycles is illustrated in figs 22, 23 and 24. fig.18 bit transfer. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl 1997 dec 16 25 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.19 definition of start and stop conditions. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.20 system configuration. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.21 acknowledgement on the i 2 c-bus. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master 1997 dec 16 26 philips semiconductors product speci?cation lcd controller/driver pcf2104x handbook, full pagewidth s a 0 s 011101 0a slave address control byte a data a data a r/w 2n 0 bytes acknowledgement from pcf2104x control byte a mgc617 p update data pointer n 0 bytes 1 byte s a 0 011101 0 pcf2104x slave address r/w 1 co 0 co fig.22 master transmits to slave receiver; write mode. 1997 dec 16 27 philips semiconductors product speci?cation lcd controller/driver pcf2104x handbook, full pagewidth s a 0 s 011101 0a slave address control byte a 1 co data a 1 1 control a r/w 0 co 2 bytes 2n 0 bytes data a acknowledgement from pcf2104x mgc618 s a 0 s 1a data a 1 p slave address data acknowledgement from pcf2104x no acknowledgement from master r/w n bytes last byte update data pointer (1) fig.23 master reads after setting word address; write word address, set rs/ rw; read data. (1) last data byte is a dummy byte (may be omitted). 1997 dec 16 28 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.24 master reads slave immediately after first byte; read mode (rs previously defined). handbook, full pagewidth mgc619 s a 0 s 1a data a 1 p slave address data acknowledgement from pcf2104x no acknowledgement from master r/w n bytes last byte update data pointer acknowledgement from master 1997 dec 16 29 philips semiconductors product speci?cation lcd controller/driver pcf2104x handbook, full pagewidth mga811 - 1 t high t r t low t hd;sta t buf sda scl t f t/f scl t su;sto start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 lsb r/w acknowledge (a) stop condition (p) protocol fig.25 i 2 c-bus timing diagram; rise and fall times refer to v il and v ih . 1997 dec 16 30 philips semiconductors product speci?cation lcd controller/driver pcf2104x 12 limiting values in accordance with the absolute maximum rating system (iec 134). 13 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). 14 dc characteristics v dd = 2.5 to 6 v; v ss =0v;v lcd =v dd - 3.5 to v dd - 9v;t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter min. max. unit v dd supply voltage - 0.5 +8.0 v v lcd lcd supply voltage v dd - 11 v dd v v i input voltage osc, rs, r/ w, e and db0 to db7 v ss - 0.5 v dd + 0.5 v v o output voltage r1 to r32, c1 to c60 and v lcd v lcd - 0.5 v dd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma i dd , i ss , i lcd v dd , v ss or v lcd current - 50 +50 ma p tot total power dissipation - 400 mw p o power dissipation per output - 100 mw t stg storage temperature - 65 +150 c symbol parameter conditions min. typ. max. unit supplies v dd supply voltage 2.5 - 6.0 v v lcd lcd supply voltage v dd - 9 - v dd - 3.5 v i dd supply current external v lcd note 1 --- i dd1 supply current 1 - 200 500 m a i dd2 supply current 2 v dd =5v; v op =9v; f osc = 150 khz; t amb =25 c - 200 300 m a i dd3 supply current 3 v dd =3v; v op =5v; f osc = 150 khz; t amb =25 c - 150 200 m a i lcd v lcd input current notes 1 and 6 - 50 100 m a v por power-on reset voltage level note 2 - 1.3 1.8 v 1997 dec 16 31 philips semiconductors product speci?cation lcd controller/driver pcf2104x notes 1. lcd outputs are open-circuit; inputs at v dd or v ss ; v 0 =v dd ; bus inactive; internal or external clock with duty cycle 50% (i dd1 only). 2. resets all logic when v dd 1997 dec 16 33 philips semiconductors product speci?cation lcd controller/driver pcf2104x 16 timing diagrams fig.26 parallel bus write operation sequence; writing data from microcontroller to pcf2104x. handbook, full pagewidth rs e db0 to db7 v v v v v v v v v v v v v t ih1 il1 ih1 il1 ih1 il1 il1 il1 ih1 il1 ih1 il1 v il1 v ih1 il1 cy t dsw h t eh pw t ah t ah t as valid data mla798 - 1 r/w fig.27 parallel bus read operation sequence; reading data from pcf2104x to microcontroller. handbook, full pagewidth rs r/w e db0 to db7 v v v v v v v v v v ih1 il1 ih1 il1 ih1 il1 ih1 il1 v ol1 v oh1 il1 t cy dhr t eh pw t ah t ah t as ih1 v ol1 v oh1 t ddr v ih1 mla799 - 1 1997 dec 16 34 philips semiconductors product speci?cation lcd controller/driver pcf2104x 17 application information fig.28 direct connection to 8-bit microcontroller; 8-bit bus. handbook, 4 columns mgc620 pcf2104x db0 to db7 e rs r/w 8 32 r1 to r32 c1 to c60 60 p20 p21 p22 p10 to p17 p80cl51 to lcd fig.29 direct connection to 8-bit microcontroller; 4-bit bus. handbook, 4 columns mgc621 pcf2104x db4 to db7 e rs r/w 4 32 r1 to r32 c1 to c60 60 p10 p11 p12 p14 to p17 p80cl51 to lcd fig.30 typical application using parallel interface. handbook, full pagewidth mgc624 v ss pcf2104x v ss v lcd v lcd v dd v dd 100 nf db0 to db7 e rs r/w 2 x 24 character lcd display (split screen) 16 c1 to c60 60 60 16 osc 100 nf r7 to r16 r25 to r32 r1 to r8 r17 to r24 1997 dec 16 35 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.31 application using i 2 c-bus interface. handbook, full pagewidth v dd v ss pcf2104x v ss v dd v lcd v lcd v lcd v lcd 100 nf 2 x 24 character lcd display (split screen) 16 c1 to c60 60 60 16 osc 100 nf mgc625 v dd v ss pcf2104x v ss v dd 100 nf 2 x 12 character lcd display 16 c1 to c60 60 osc 100 nf r1 to r16 r17 to r24 r1 to r16 sa0 sa0 v ss v dd v dd v dd scl sda master transmitter pcf84c81 1997 dec 16 36 philips semiconductors product speci?cation lcd controller/driver pcf2104x 17.1 8-bit operation, 2 12 display using internal reset table 7 shows an example of a 1-line display in 8-bit operation. the pcf2104x functions must be set by the function set instruction prior to display. since the display data ram can store data for 80 characters, the ram can be used for advertising displays when combined with display shift operation. since the display shift operation changes the display position only and ddram contents remain unchanged. display data entered first can be displayed when the return home instruction is performed. 17.2 4-bit operation, 2 12 display using internal reset the program must set functions prior to 4-bit operation. table 6 shows an example. when power is turned on, 8-bit operation is automatically selected and the pcf2104x attempts to perform the first write as an 8-bit operation. since nothing is connected to db0 to db3, a rewrite is then required. however, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see table 6 step 3). thus, db4 to db7 of the function set are written twice. 17.3 8-bit operation, 2 24 display for a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. thus, if there are only 8 characters in the first line, the ddram address must be set after the eighth character is completed (see table 8). it should be noted that both lines of the display are always shifted together, data does not shift from one line to the other. 17.4 i 2 c operation, 2 12 display a control byte is required with most instructions (see table 9). 17.5 initializing by instruction if the power supply conditions for correctly operating the internal reset circuit are not met, the pcf2104x must be initialized by instruction. tables 10 and 11 show how this may be performed for 8-bit and 4-bit operation. 1997 dec 16 37 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 6 4-bit operation, 1-line display example; using internal reset step instruction display operation 1 power supply on (pcf2104x is initialized by the internal reset circuit). initialized. no display appears. 2 function set: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 0 sets to 4-bit operation. in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write. 3 function set: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 0 sets to 4-bit operation, selects 2 12 display. rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0 4-bit operation starts from this point and resetting is needed. 4 display on/off control: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0 turns on display and cursor. rs = 0; r/ w = 0; db7 = 1; db6 = 1; db5 = 1; db4 = 0 entire display is blank after initialization. 5 entry mode set: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the dd/cgram. rs = 0; r/ w = 0; db7 = 0; db6 = 1; db5 = 1; db4 = 0 display is not shifted. 6 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 1 p_ writes p. the ddram has already been selected by initialization at power-on. rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 1; db4 = 0 the cursor is incremented by 1 and shifted to the right. 1997 dec 16 38 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 7 8-bit operation, 1-line display example; using internal reset (character set a) step instruction display operation 1 power supply on (pcf2104x is initialized by the internal reset function). initialized. no display appears. 2 function set: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1; db3 = 0; db2 = 0; db1 = 0; db0 = 0 sets to 8-bit operation, selects 2 12 display. 3 display mode on/off control: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 1; db0 = 0 _ turns on display and cursor. entire display is blank after initialization. 4 entry mode set: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 1; db1 = 1; db0 = 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the dd/cgram. display is not shifted. 5 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 1; db3 = 0; db2 = 0; db1 = 0; db0 = 0 p_ writes p. the ddram has already been selected by initialization at power-on. the cursor is incremented by 1 and shifted to the right. 6 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 1; db4 = 1; db3 = 1; db2 = 0; db1 = 0; db0 = 0 ph_ writes h. 7 | | | 8 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 1; db3 = 0; db2 = 0; db1 = 1; db0 = 1 philips_ writes s. 9 entry mode set: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 1; db1 = 1; db0 = 1 philips_ sets mode for display shift at the time of write. 10 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 0; db3 = 0; db2 = 0; db1 = 0; db0 = 0 hilips _ writes space. 11 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 0; db0 = 1 ilips m_ writes m. 12 | | | 1997 dec 16 39 philips semiconductors product speci?cation lcd controller/driver pcf2104x 13 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 1; db0 = 1 microko writes o. 14 cursor or display shift: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 1; db3 = 0; db2 = 0; db1 = 0; db0 = 0 microk o shifts only the cursor position to the left. 15 cursor or display shift: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 1; db3 = 0; db2 = 0; db1 = 0; db0 = 0 micro ko shifts only the cursor position to the left. 16 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 0; db2 = 0; db1 = 1; db0 = 1 icroc o writes c correction. the display moves to the left. 17 cursor or display shift: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 1; db3 = 1; db2 = 1; db1 = 0; db0 = 0 microc o shifts the display and cursor to the right. 18 cursor or display shift: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 1; db3 = 0; db2 = 1; db1 = 0; db0 = 0 microco_ shifts only the cursor to the right. 19 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 0; db0 = 1 icrocom_ writes m. 20 | | | 21 return home: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 0; db1 = 1; db0 = 0 philips m returns both display and cursor to the original position (address 0). step instruction display operation 1997 dec 16 40 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 8 8-bit operation, 2-line display example; using internal reset step instruction display operation 1 power supply on (pcf2104x is initialized by the internal reset function). initialized. no display appears. 2 function set: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1; db3 = 1; db2 = 0; db1 = 0; db0 = 0 sets to 8-bit operation, selects 2 24 display 3 display on/off control: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 1; db0 = 0 _ turns on display and cursor. entire display is blank after initialization. 4 entry mode set: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 1; db1 = 1; db0 = 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the cg/ddram. display is not shifted. 5 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 1; db3 = 0; db2 = 0; db1 = 0; db0 = 0 p_ writes p. the ddram has already been selected by initialization at power-on. the cursor is incremented by 1 and shifted to the right. 6 | | | 7 write data to cgram/ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 1; db3 = 0; db2 = 0; db1 = 1; db0 = 1 philips_ writes s. 8 set ddram address: rs = 0; r/ w = 0; db7 = 1; db6 = 1; db5 = 0; db4 = 0; db3 = 0; db2 = 0; db1 = 0; db0 = 0 philips sets ddram address to position the cursor at the head of the 2nd line. _ 9 write data to cgram/ ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 0; db0 = 1 philips writes m. m_ 10 | | | 11 write data to cgram/ ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 1; db0 = 1 philips writes o. microco_ 12 write data to cgram/ ddram: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 1; db1 = 1; db0 = 1 philips sets mode for display shift at the time of write. microco_ 1997 dec 16 41 philips semiconductors product speci?cation lcd controller/driver pcf2104x 13 write data to cgram/ ddram: rs = 1; r/ w = 0; db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 0; db0 = 1 hilips writes m. display is shifted to the left. the ?rst and second lines shift together. icrocom_ 14 | | | 15 return home: rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 0; db1 = 1; db0 = 0 philips returns both display and cursor to the original position (address 0). microcom step instruction display operation 1997 dec 16 42 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 9 example of i 2 c-bus operation; 1-line display (using internal reset, assuming sa0 = v ss ; note 1) step i 2 c-bus byte display operation 1i 2 c-bus start initialized. no display appears. 2 slave address for write: sa6 = 0; sa5 = 1; sa4 = 1; sa3 = 1; sa2 = 0; sa1 = 1; sa0 = 0; r/ w = 0; ack = 1 during the acknowledge cycle sda will be pulled-down by the pcf2104x. 3 send a control byte for function set: co = 0; rs = 0; r/ w = 0; ack = 1 control byte sets rs and r/ w for following data bytes. 4 function set: db7 = 0; db6 = 0; db5 = 1; db4 = x; db3 = 0; db2 = 0; db1 = 0; db0 = 0; ack = 1 selects 1-line display; scl pulse during acknowledge cycle starts execution of instruction. 5 display on/off control: db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 1; db2 = 1; db1 = 1; db0 = 0; ack = 1 _ turns on display and cursor. entire display shows character hex 20 (blank in ascii-like character sets). 6 entry mode set: db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 1; db1 = 1; db0 = 0; ack = 1 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the ddram or cgram. display is not shifted. 7i 2 c-bus start _ for writing data to ddram, rs must be set to 1. therefore a control byte is needed. 8 slave address for write: sa6 = 0; sa5 = 1; sa4 = 1; sa3 = 1; sa2 = 0; sa1 = 1; sa0 = 0; r/ w = 0; ack = 1 _ 9 send a control byte for write data: co = 0; rs = 1; r/ w = 0; ack = 1 _ 10 write data to ddram: db7 = 0; db6 = 1; db5 = 0; db4 = 1; db3 = 0; db2 = 0; db1 = 0; db0 = 0; ack = 1 p_ writes p. the ddram has been selected at power-up. the cursor is incremented by 1 and shifted to the right. 11 write data to ddram: db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 0; db1 = 0; db0 = 0; ack = 1 ph_ writes h. 12 to 15 | | | | 16 write data to ddram: db7 = 0; db6 = 1; db5 = 0; db4 = 1; db3 = 0; db2 = 0; db1 = 1; db0 = 1; ack = 1 philips_ writes s. 1997 dec 16 43 philips semiconductors product speci?cation lcd controller/driver pcf2104x notes 1. x = dont care. 2. sda is left at high-impedance by the microcontroller during the read acknowledge. 17 (optional i 2 c-bus stop) i 2 c-bus start + slave address for write (as step 8) philips_ 18 control byte: co = 1; rs = 0; r/ w = 0; ack = 1 philips_ 19 return home: db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 0; db1 = 1; db0 = 0; ack = 1 philips sets ddram address 0 in address counter. (also returns shifted display to original position. ddram contents unchanged). this instruction does not update the data register (dr). 20 control byte for read: co = 0; rs = 1; r/ w = 1; ack = 1 philips ddram content will be read from following instructions. the r/ w has to be set to 1 while still in i 2 c-bus write mode. 21 i 2 c-bus start philips 22 slave address for read: sa6 = 0; sa5 = 1; sa4 = 1; sa3 = 1; sa2 = 0; sa1 = 1; sa0 = 0; r/ w = 1; ack = 1 p hilips during the acknowledge cycle the content of the dr is loaded into the internal i 2 c-bus interface to be shifted out. in the previous instruction neither a set address nor a read data has been performed. therefore the content of the dr was unknown. 23 read data: 8 scl + master acknowledge; note 2: db7 = x; db6 = x; db5 = x; db4 = x; db3 = x; db2 = x; db1 = x; db0 = x; ack = 1 ph ilips 8 scl; content loaded into interface during previous acknowledge cycle is shifted out over sda. msb is db7. during master acknowledge content of ddram address 01 is loaded into the i 2 c-bus interface. 24 read data: 8 scl + master acknowledge; note 2: db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 0; db1 = 0; db0 = 0; ack = 0 phi lips 8 scl; code of letter h is read ?rst. during master acknowledge code of i is loaded into the i 2 c-bus interface. 25 read data: 8 scl + no master acknowledge; note 2: db7 = 0; db6 = 1; db5 = 0; db4 = 0; db3 = 1; db2 = 0; db1 = 0; db0 = 1; ack = 1 phi lips no master acknowledge; after the content of the i 2 c-bus interface register is shifted out no internal action is performed. no new data is loaded to the interface register, data register (dr) is not updated, address counter (ac) is not incremented and cursor is not shifted. 26 i 2 c stop phi lips step i 2 c-bus byte display operation 1997 dec 16 44 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 10 initialization by instruction, 8-bit interface (note 1) note 1. x = dont care. step description power-on or unknown state | wait 2 ms after v dd rises above v por | rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1; db3 = x; db2 = x; db1 = x; db0 = x bf cannot be checked before this instruction. function set (interface is 8-bits long). | wait 2 ms | rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1; db3 = x; db2 = x; db1 = x; db0 = x bf cannot be checked before this instruction.function set (interface is 8-bits long). | wait more than 40 m s | rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1; db3 = x; db2 = x; db1 = x; db0 = x bf cannot be checked before this instruction. function set (interface is 8-bits long). | | bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is the speci?ed instruction time (see table 3). rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1; db3 = n; db2 = m; db1 = x; db0 = 0 function set (interface is 8-bits long). specify the number of display lines. rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 1; db2 = 0; db1 = 0; db0 = 0 display off. rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 0; db1 = 0; db0 = 1 clear display. rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0; db3 = 0; db2 = 1; db1 = i/d; db0 = s entry mode set. | initialization ends 1997 dec 16 45 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 11 initialization by instruction, 4-bit interface. not applicable for i 2 c-bus operation step description power-on or unknown state | wait 2 ms after v dd rises above v por | rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1 bf cannot be checked before this instruction. function set (interface is 8-bits long). | wait 2 ms | rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1 bf cannot be checked before this instruction. function set (interface is 8-bits long). | wait 40 m s | rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 1 bf cannot be checked before this instruction. function set (interface is 8-bits long). | | bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is the speci?ed instruction time (see table 3). rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 0 function set (set interface to 4-bits long). interface is 8-bits long. rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 1; db4 = 0 function set (interface is 4-bits long). rs = 0; r/ w = 0; db7 = n; db6 = m; db5 = 0; db4 = 0 specify number of display lines and voltage generator characteristic. rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0 display off. rs = 0; r/ w = 0; db7 = 1; db6 = 0; db5 = 0; db4 = 0 rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0 clear display. rs = 0; r/ w = 0; db7 = 1; db6 = 0; db5 = 0; db4 = 0 rs = 0; r/ w = 0; db7 = 0; db6 = 0; db5 = 0; db4 = 0 entry mode set. rs = 0; r/ w = 0; db7 = 0; db6 = 1; db5 = i/d; db4 = s | initialization ends 1997 dec 16 46 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.32 example of 4 12 display layout (pcf2104x). handbook, full pagewidth c1 15 46 60 c16 45 r8 to r1 r9 to r16 r32 to r25 r17 to r24 display layout: rows display layout: columns pcf2104x column output numbers pcf2104x column output numbers lcd column numbers mgc623 13160 dot matrix lcd 1997 dec 16 47 philips semiconductors product speci?cation lcd controller/driver pcf2104x handbook, full pagewidth 1 to 8 16 to 9 mlb898 display glass dot matrix column layout row layout 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2 lines by 12 characters display fig.33 display example (pcf2104x); 2 lines by 12 characters. 1997 dec 16 48 philips semiconductors product speci?cation lcd controller/driver pcf2104x fig.34 chip-on-glass application. handbook, full pagewidth mgc626 pcf2104x chip-on-glass 4 line by 12 character r1 r8 r17 r24 r9 r16 r25 r32 2104 c1 r9 c60 scl sda v lcd dd v v ss 1997 dec 16 49 philips semiconductors product speci?cation lcd controller/driver pcf2104x 18 bonding pad locations fig.35 bonding pad locations. chip dimensions: approximately 5.10 5.63 mm. gold bump dimensions: approximately 89 89 25 m m. handbook, full pagewidth pcf2104x ? 5.63 mm ? 5.10 mm x y 0 0 c58 c57 c56 c55 c54 c59 r21 r20 r19 r18 r17 c60 r22 r24 r23 r29 r5 r32 r31 r30 r6 r8 r7 c17 c18 c19 c20 c21 c22 c16 c10 c11 c12 c13 c14 c15 c9 c7 c8 c6 c2 c3 c4 c5 r11 r12 r14 r13 c1 r10 r9 sa0 v ss v dd osc c35 c36 c37 c38 c39 c40 c41 c42 c43 c44 c45 c46 c48 c49 c47 c50 c51 c23 c24 c25 c26 c27 c28 c29 c31 c32 c30 c33 c34 c52 c53 rs r/w t1 db7 db6 db5 db4 db3 db2 db1 db0 sda v lcd r15 r16 r25 r26 r27 r28 r1 r3 r4 r2 scl e 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627 86 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 28 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 36 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 mgc628 1997 dec 16 50 philips semiconductors product speci?cation lcd controller/driver pcf2104x table 12 bonding pad locations (dimensions in m m). all x/y coordinates are referenced to centre of chip, see fig.35 symbol pad x y osc 1 - 2184.5 - 2637 v dd 2 - 2024.5 - 2637 sa0 3 - 1864.5 - 2637 v ss 4 - 1704.5 - 2637 r8 5 - 1339 - 2637 r7 6 - 1179 - 2637 r6 7 - 1019 - 2637 r5 8 - 859 - 2637 r32 9 - 699 - 2637 r31 10 - 539 - 2637 r30 11 - 379 - 2637 r29 12 - 219 - 2637 r24 13 - 59 - 2637 r23 14 101 - 2637 r22 15 261 - 2637 r21 16 421 - 2637 r20 17 581 - 2637 r19 18 741 - 2637 r18 19 901 - 2637 r17 20 1061 - 2637 c60 21 1221 - 2637 c59 22 1381 - 2637 c58 23 1541 - 2637 c57 24 1701 - 2637 c56 25 1861 - 2637 c55 26 2021 - 2637 c54 27 2181 - 2637 c53 28 2350 - 2445 c52 29 2350 - 2285 c51 30 2350 - 2125 c50 31 2350 - 1965 c49 32 2350 - 1805 c48 33 2350 - 1645 c47 34 2350 - 1485 c46 35 2350 - 1325 c45 36 2350 - 1165 c44 37 2350 - 1005 c43 38 2350 - 845 c42 39 2350 - 685 c41 40 2350 - 525 c40 41 2350 - 365 c39 42 2350 - 205 c38 43 2350 - 45 c37 44 2350 115 c36 45 2350 275 c35 46 2350 435 c34 47 2350 595 c33 48 2350 755 c32 49 2350 915 c31 50 2350 1075 c30 51 2350 1235 c29 52 2350 1395 c28 53 2350 1555 c27 54 2350 1715 c26 55 2350 1875 c25 56 2350 2035 c24 57 2350 2195 c23 58 2350 2355 c22 59 2185 2637.5 c21 60 2025 2637.5 c20 61 1865 2637.5 c19 62 1705 2637.5 c18 63 1545 2637.5 c17 64 1385 2637.5 c16 65 1225 2637.5 c15 66 1065 2637.5 c14 67 905 2637.5 c13 68 745 2637.5 c12 69 585 2637.5 c11 70 425 2637.5 c10 71 265 2637.5 c9 72 105 2637.5 c8 73 - 55 2637.5 c7 74 - 215 2637.5 c6 75 - 375 2637.5 c5 76 - 535 2637.5 symbol pad x y 1997 dec 16 51 philips semiconductors product speci?cation lcd controller/driver pcf2104x c4 77 - 695 2637.5 c3 78 - 855 2637.5 c2 79 - 1015 2637.5 c1 80 - 1175 2637.5 r9 81 - 1385 2637.5 r10 82 - 1545 2637.5 r11 83 - 1705 2637.5 r12 84 - 1865 2637.5 r13 85 - 2025 2637.5 r14 86 - 2185 2637.5 r15 87 - 2349 2308 r16 88 - 2349 2148 r25 89 - 2349 1988 r26 90 - 2349 1828 r27 91 - 2349 1668 r28 92 - 2349 1508 r1 93 - 2349 1348 r2 94 - 2349 1188 r3 95 - 2349 1028 r4 96 - 2349 868 scl 97 - 2349 632 e98 - 2349 472 rs 99 - 2349 312 r/ w 100 - 2349 142 t1 101 - 2349 - 34 db7 102 - 2349 - 233 db6 103 - 2349 - 393 db5 104 - 2349 - 668 db4 105 - 2349 - 828 db3 106 - 2349 - 1103 db2 107 - 2349 - 1263 db1 108 - 2349 - 1538 db0 109 - 2349 - 1698 sda 110 - 2349 - 1933 v lcd 111 - 2349 - 2453 recpat f - 2327.5 2427.5 recpat c - 2027.5 - 2512.5 recpat c 1982.5 2297.5 symbol pad x y 1997 dec 16 52 philips semiconductors product speci?cation lcd controller/driver pcf2104x 19 definitions 20 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 21 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1997 dec 16 53 philips semiconductors product speci?cation lcd controller/driver pcf2104x notes 1997 dec 16 54 philips semiconductors product speci?cation lcd controller/driver pcf2104x notes 1997 dec 16 55 philips semiconductors product speci?cation lcd controller/driver pcf2104x notes internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2870, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417067/1200/04/pp56 date of release: 1997 dec 16 document order number: 9397 750 02924 |
Price & Availability of PCF2104CU7
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |